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Applied Materials Targets 'Memory Wall' in AI Era...Presents Solutions Across D-RAM, HBM, and Packaging

Google 우선 소스Published2026.08.31 16:56


Integrated Optimization of Materials, Equipment, Process, and Packaging Enhances Next-Generation AI Semiconductor Performance

Strengthens Joint Development Including Long-Term Supply Chain Cooperation Tailored to Customer Production Capacity Expansion


In the artificial intelligence (AI) era, semiconductor industry competition hinges on 'data movement' rather than 'computation'. As AI models grow larger, power consumption and memory bottlenecks emerge as critical issues limiting system performance. Against this backdrop, Applied Materials is putting forward a strategy to support next-generation AI semiconductor performance, power efficiency, and productivity improvements by leading with an integrated portfolio spanning D-RAM device innovation through HBM (high-bandwidth memory), hybrid bonding, and co-packaged optics (CPO).


Applied Materials Korea held a 'D-RAM and Advanced Packaging Media Briefing for the AI Era' on the 31st at the Oakwood Premier COEX in Seoul, introducing structural changes in the semiconductor industry and technology roadmaps resulting from AI expansion.


The event was attended by Park Gwang-seon, Representative of Applied Materials Korea, and Mukund Srinivasan, Vice President of Applied Materials Group.


The key message of the event was clear: in the AI era, competition can no longer be based solely on individual chip performance; instead, logic, memory, and packaging must be optimized as a single system.


Vice President Mukund identified 'energy efficiency' and 'production capacity expansion' as the most pressing challenges facing the AI industry. As computational demand in AI models skyrockets, power consumption for data movement is surging, and the industry-wide solution to address this is '3D scaling', he explained. Three-dimensional structures such as GAA (gate-all-around) play key roles in logic, stacking technology such as HBM in memory, and 2.5D and 3D integration technology in packaging, according to the analysis.


Within these changes, Applied emphasized its role not as a mere equipment supplier but as a 'technology platform provider'. In particular, it presented four innovation pillars as key elements for implementing 3D scaling: new materials, selective deposition and etching processes, angstrom-level process control and metrology, and process integration optimization. With logic processes becoming more complex at over 2,000 steps and memory processes exceeding 1,200 steps, the connectivity of the overall process and co-optimization become increasingly important beyond individual equipment performance alone, the company explained.


Of particular note was the strategy for solving the 'memory wall', identified as the greatest challenge for AI semiconductors. As AI processor performance improvement outpaces memory development speed, how quickly data can be supplied now determines system performance. Accordingly, Applied is concentrating on extending technologies validated in leading-edge logic to D-RAM. The strategy involves applying key logic technologies such as epitaxy, metal interconnects, and CMP to D-RAM peripheral circuits to simultaneously enhance speed and power efficiency.


Regarding D-RAM technology roadmaps, various technology evolution directions were presented, including CBA (CMOS Bonded Array), 4F² vertical transistor structures, and long-term 3D D-RAM development.


Vice President Mukund stated, "3D D-RAM does not completely replace EUV, but it can significantly reduce EUV consumption," and added, "We are confident in individual materials and process technologies; the remaining task is to integrate them effectively."


In the HBM and advanced packaging fields, hybrid bonding emerged as a key concept.


While the conventional microbump approach has physical limitations on inter-chip spacing, hybrid bonding can reduce the distance between dies to nearly zero level, dramatically enhancing I/O density, power efficiency, and bandwidth.


Applied disclosed that it has secured a broad technology portfolio including the hybrid bonding system 'Kinex', CMP, copper deposition, and metrology and inspection solutions to achieve this.


The company also expressed high expectations for co-packaged optics (CPO).


CPO is a technology that replaces some internal electrical wiring within packages with optical signal-based connections and is regarded as a key technology for next-generation AI data centers.


Applied is developing new materials for waveguides for optical signal transmission and related process technologies, and views hybrid bonding technology as a foundational technology for CPO implementation, working closely with customers, the company explained.


The strategic importance of the Korean market was also emphasized.


Representative Park Gwang-seon evaluated Samsung Electronics and SK Hynix as at the center of the global AI memory ecosystem and projected that Korea's importance will grow further.


He stated, "Korean companies hold a very significant position in the HBM and advanced memory market," and added, "As the AI era becomes mainstream, Korea will emerge as a strategic hub encompassing not only memory but also advanced packaging and leading-edge logic."


To support this, Applied is strengthening long-term supply chain cooperation tailored to customer production capacity expansion, supporting expansion of global production bases, and enhancing joint development of next-generation packaging.


The company is also establishing a joint research and development system with customers, universities, and partner companies through the EPIC (Equipment and Process Innovation and Commercialization) platform.


Currently, major semiconductor companies including Samsung Electronics and SK Hynix are participating in EPIC projects, and the plan is to connect the Silicon Valley EPIC Center with ACC Korea in Osan to shorten the timeframe from research and development through mass production verification.


Ultimately, the AI-era solution presented by Applied Materials lies not in 'more transistors' but in 'more efficient data movement'.


The approach binds D-RAM, HBM, advanced packaging, and optical interconnect technology as continuous innovation challenges and pursues integrated optimization of materials, equipment, process, and packaging to enhance AI performance.

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